5 search results - page 1 / 1 » L1 Cache and TLB Enhancements to the RAMpage Memory Hierarch... |
APCSAC
2003
IEEE
14 years 4 months ago
2003
IEEE
The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main mem...
WMPI
2004
ACM
14 years 4 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
DAC
2012
ACM
12 years 1 months ago
2012
ACM
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more ...
CF
2010
ACM
14 years 2 months ago
2010
ACM
Cache memories currently treat all blocks as if they were equally important, but this assumption of equally importance is not always valid. For instance, not all blocks deserve to...
ASPDAC
2004
ACM
14 years 2 months ago
2004
ACM
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...