33 search results - page 1 / 7 » LOTTERYBUS: A New High-Performance Communication Architectur... |
DAC
2001
ACM
14 years 8 months ago
2001
ACM
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
TVLSI
2008
13 years 6 months ago
2008
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
CCGRID
2006
IEEE
13 years 10 months ago
2006
IEEE
MPICH2 provides a layered architecture for implementing MPI-2. In this paper, we provide a new design for implementing MPI-2 over InfiniBand by extending the MPICH2 ADI3 layer. Ou...
DMIN
2009
13 years 4 months ago
2009
While the emerging field of privacy preserving data mining (PPDM) will enable many new data mining applications, it suffers from several practical difficulties. PPDM algorithms are...
SI3D
1995
ACM
13 years 10 months ago
1995
ACM
Interactive graphics applications have long been challenging graphics system designers by demanding machines that can provide ever increasing polygon rendering performance. Anothe...