33 search results - page 3 / 7 » LOTTERYBUS: A New High-Performance Communication Architectur... |
ICDE
2009
IEEE
14 years 8 months ago
2009
IEEE
We present the architectural design and recent performance optimizations of a state of the art commercial database replication technology provided in Oracle Streams. The underlying...
PPL
2008
13 years 7 months ago
2008
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
To exploit the potential of multicore architectures, recent dense linear algebra libraries have used tile algorithms, which consist in scheduling a Directed Acyclic Graph (DAG) of...
ASYNC
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-perf...
IPPS
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper develops a plug-and-play reusable LogGP model that can be used to predict the runtime and scaling behavior of different MPI-based pipelined wavefront applications runni...