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» LTL Model Checking for Modular Petri Nets
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ASPDAC
2007
ACM
158views Hardware» more  ASPDAC 2007»
13 years 10 months ago
Symbolic Model Checking of Analog/Mixed-Signal Circuits
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
David Walter, Scott Little, Nicholas Seegmiller, C...
FOSSACS
2010
Springer
14 years 1 months ago
On the Relationship between Spatial Logics and Behavioral Simulations
Abstract. Spatial logics have been introduced to reason about distributed computation in models for concurrency. We first define a spatial logic for a general class of infinite-...
Lucia Acciai, Michele Boreale, Gianluigi Zavattaro
SPIN
2009
Springer
14 years 1 months ago
Identifying Modeling Errors in Signatures by Model Checking
: Most intrusion detection systems deployed today apply misuse detection as analysis method. Misuse detection searches for attack traces in the recorded audit data using predefined...
Sebastian Schmerl, Michael Vogel, Hartmut Kön...
ATVA
2005
Springer
132views Hardware» more  ATVA 2005»
14 years 7 days ago
Flat Counter Automata Almost Everywhere!
Abstract. This paper argues that flatness appears as a central notion in the verification of counter automata. A counter automaton is called flat when its control graph can be ...
Jérôme Leroux, Grégoire Sutre
SPIN
2001
Springer
13 years 11 months ago
From Model Checking to a Temporal Proof
ions Using SPIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Marsha Chechik, Benet Devereux, Arie Gurfinkel (University of Toronto) Imp...
Doron Peled, Lenore D. Zuck