384 search results - page 4 / 77 » Latch Modeling for Statistical Timing Analysis |
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
Statistical static timing analysis (SSTA) is emerging as a solution for predicting the timing characteristics of digital circuits under process variability. For computing the stat...
ACL
2012
11 years 10 months ago
2012
Long-span features, such as syntax, can improve language models for tasks such as speech recognition and machine translation. However, these language models can be difficult to u...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. Noise analysis techniques can detect some of such noise faults, but accu...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
Statistical static timing analysis (SSTA) has become a key method for analyzing the effect of process variation in aggressively scaled CMOS technologies. Much research has focused...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
