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DATE
2009
IEEE
88views Hardware» more  DATE 2009»
14 years 2 months ago
Latency criticality aware on-chip communication
—Packet-switched interconnect fabric is a promising on-chip communication solution for many-core architectures. It offers high throughput and excellent scalability for on-chip da...
Zheng Li, Jie Wu, Li Shang, Robert P. Dick, Yihe S...
INFOCOM
2006
IEEE
14 years 1 months ago
Time Synchronization for High Latency Acoustic Networks
— Distributed time synchronization is an important part of a sensor network where sensing and actuation must be coordinated across multiple nodes. Several time synchronization pr...
Affan A. Syed, John S. Heidemann
EUROPAR
2001
Springer
14 years 6 days ago
Optimal Polling for Latency-Throughput Tradeoffs in Queue-Based Network Interfaces for Clusters
We consider a networking subsystem for message–passing clusters that uses two unidirectional queues for data transfers between the network interface card (NIC) and the lower prot...
Dmitry Ponomarev, Kanad Ghose, Eugeny Saksonov
DATE
2008
IEEE
115views Hardware» more  DATE 2008»
14 years 2 months ago
Synthesizing Synchronous Elastic Flow Networks
This paper describes an implementation language and synthesis system for automatically generating latency insensitive synchronous digital designs. These designs decouple behaviora...
Greg Hoover, Forrest Brewer
ASYNC
2003
IEEE
119views Hardware» more  ASYNC 2003»
14 years 1 months ago
Asynchronous DRAM Design and Synthesis
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long a...
Virantha N. Ekanayake, Rajit Manohar