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MEMOCODE
2007
IEEE
14 years 4 months ago
Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design
—With the arrival of nanometer technologies wire delays are no longer negligible with respect to gate delays, and timing-closure becomes a major challenge to System-on-Chip desig...
Cheng-Hong Li, Rebecca L. Collins, Sampada Sonalka...
DAC
2000
ACM
14 years 10 months ago
Performance analysis and optimization of latency insensitive systems
Latency insensitive design has been recently proposed in literature as a way to design complex digital systems, whose functional behavior is robust with respect to arbitrary varia...
Luca P. Carloni, Alberto L. Sangiovanni-Vincentell...
CDES
2006
101views Hardware» more  CDES 2006»
13 years 11 months ago
Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors
- Error detection plays an important role in fault-tolerant computer systems. Two primary parameters concerned for error detection are the latency and coverage. In this paper, a ne...
Yung-Yuan Chen, Kuen-Long Leu, Li-Wen Lin
HPDC
2002
IEEE
14 years 2 months ago
Evaluating Web Services Based Implementations of GridRPC
GridRPC is a class of Grid middleware for scientific computing. Interoperability has been an important issue, because current GridRPC systems each employ its own protocol. Web se...
Satoshi Shirasuna, Hidemoto Nakada, Satoshi Matsuo...
EUROPAR
2003
Springer
14 years 3 months ago
Implementation and Performance Evaluation of M-VIA on AceNIC Gigabit Ethernet Card
This paper describes the implementation and performance of M-VIA on the AceNIC Gigabit Ethernet card. The AceNIC adapter has several notable hardware features for high-speed commun...
In-Su Yoon, Sang-Hwa Chung, Ben Lee, Hyuk-Chul Kwo...