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» Lattice-Valued Binary Decision Diagrams
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DSD
2007
IEEE
87views Hardware» more  DSD 2007»
14 years 1 months ago
On the Construction of Small Fully Testable Circuits with Low Depth
During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small ...
Görschwin Fey, Anna Bernasconi, Valentina Cir...
ISCAS
2006
IEEE
94views Hardware» more  ISCAS 2006»
14 years 1 months ago
On the sensitivity of BDDs with respect to path-related objective functions
— Reduced ordered Binary Decision Diagrams (BDDs) are a data structure for efficient representation and manipulation of Boolean functions. They are frequently used in logic synt...
Rüdiger Ebendt, Rolf Drechsler
ACSD
2005
IEEE
71views Hardware» more  ACSD 2005»
14 years 1 months ago
Maximal Causality Analysis
Perfectly synchronous systems immediately react to the inputs of their environment, which may lead to so-called causality cycles between actions and their trigger conditions. Algo...
Klaus Schneider, Jens Brandt, Tobias Schüle, ...
ISAAC
2003
Springer
144views Algorithms» more  ISAAC 2003»
14 years 18 days ago
Biconnectivity on Symbolically Represented Graphs: A Linear Solution
Abstract. We define an algorithm for determining, in a linear number of symbolic steps, the biconnected components of a graph implicitly represented with Ordered Binary Decision D...
Raffaella Gentilini, Alberto Policriti
TACAS
2001
Springer
92views Algorithms» more  TACAS 2001»
13 years 12 months ago
Language Containment Checking with Nondeterministic BDDs
Abstract. Checking for language containment between nondeterministic ω-automata is a central task in automata-based hierarchical verification. We present a symbolic procedure for...
Bernd Finkbeiner