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ASPDAC
2000
ACM
95views Hardware» more  ASPDAC 2000»
14 years 12 days ago
FSM decomposition by direct circuit manipulation applied to low power design
Abstract— Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significa...
José C. Monteiro, Arlindo L. Oliveira
FCCM
1999
IEEE
146views VLSI» more  FCCM 1999»
14 years 10 days ago
Sepia: Scalable 3D Compositing Using PCI Pamette
We have implemented an image combining architecture that allows distributed rendering of a partitioned data set at interactive rates. The architecture achieves real-time frame rat...
Laurent Moll, Mark Shand, Alan Heirich
ICCAD
1997
IEEE
99views Hardware» more  ICCAD 1997»
14 years 7 days ago
High-level area and power estimation for VLSI circuits
High-level power estimation, when given only a high-level design specification such as a functional or RTL description, requires high-level estimation of the circuit average acti...
Mahadevamurty Nemani, Farid N. Najm
LPNMR
1993
Springer
14 years 3 days ago
Negation as Partial Failure
We present a logic programming language which uses a four-valued bilattice as the underlying framework for semantics of programs. The two orderings of the bilattice reflect the c...
Bamshad Mobasher, Jacek Leszczylowski, Don Pigozzi
POPL
1993
ACM
14 years 3 days ago
Graph Types
e data structures are abstractions of simple records and pointers. They impose a shape invariant, which is verified at compiletime and exploited to automatically generate code fo...
Nils Klarlund, Michael I. Schwartzbach