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DAC
2009
ACM
14 years 10 months ago
Double patterning lithography friendly detailed routing with redundant via consideration
In double patterning lithography (DPL), coloring conflict and stitch minimization are the two main challenges. Post layout decomposition algorithm [1] [2]may not be enough to achi...
Kun Yuan, Katrina Lu, David Z. Pan
MOBISYS
2006
ACM
14 years 8 months ago
Measurement driven deployment of a two-tier urban mesh access network
Multihop wireless mesh networks can provide Internet access over a wide area with minimal infrastructure expenditure. In this work, we present a measurement driven deployment stra...
Joseph Camp, Joshua Robinson, Christopher Steger, ...
ISORC
2009
IEEE
14 years 3 months ago
Component Based Middleware-Synthesis for AUTOSAR Basic Software
Distributed real-time automotive embedded systems have to be highly dependable as well as cost-efficient due to the large number of manufactured units. To close the gap between r...
Dietmar Schreiner, Markus Schordan, Karl M. Gö...
ASPLOS
2008
ACM
13 years 11 months ago
Adapting to intermittent faults in multicore systems
Future multicore processors will be more susceptible to a variety of hardware failures. In particular, intermittent faults, caused in part by manufacturing, thermal, and voltage v...
Philip M. Wells, Koushik Chakraborty, Gurindar S. ...
ISQED
2010
IEEE
141views Hardware» more  ISQED 2010»
14 years 3 months ago
Assessing chip-level impact of double patterning lithography
—Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology optio...
Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topalog...