Assessing chip-level impact of double patterning lithography

—Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology options such as high refractive index materials, extreme ultraviolet (EUV), or e-beam lithography. DPL implements patterns on a single layer using either additional masks (e.g., double exposure or double patterning) or many additional processing steps (e.g., spacer double patterning). Overlay between the two layers introduces additional variability in both front-end-of-line (FEOL) and back-end-of-line (BEOL) by means of coupling capacitance variation. FEOL variability can be incorporated into standard characterization. However, the impacts of overlay in BEOL require new circuit analysis techniques. Furthermore, such techniques can guide technology developers toward DPL technology options that will have least variability impact on circuit performance. Today, the industry is nearing a critical juncture for choosing ...

• Type: Conference
• Year: 2010
• Where: ISQED
• Authors: Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topaloglu
• Keywords: Double Patterning, DPL Technology Options, Hardware, ISQED 2010, Patterning Lithography