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GLVLSI
2006
IEEE
115views VLSI» more  GLVLSI 2006»
14 years 1 months ago
Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
Song Peng, Rajit Manohar
MMS
2008
13 years 7 months ago
The canonical expression of the drama product manufacturing processes
As the broadcast industry is evolving toward IT-based facilities, the production workflows and their associated production metadata should similarly take advantage of IT commoditi...
Dieter Van Rijsselbergen, Barbara Van De Keer, Rik...
ASPDAC
2012
ACM
238views Hardware» more  ASPDAC 2012»
12 years 3 months ago
Design for manufacturability and reliability for TSV-based 3D ICs
—The 3D IC integration using through-silicon-vias (TSV) has gained tremendous momentum recently for industry adoption. However, as TSV involves disruptive manufacturing technolog...
David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Mo...
SLIP
2009
ACM
14 years 2 months ago
Is overlay error more important than interconnect variations in double patterning?
Double patterning lithography seems to be a prominent choice for 32nm and 22nm technologies. Double patterning lithography techniques require additional masks for a single interco...
Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topalog...
DATE
2002
IEEE
95views Hardware» more  DATE 2002»
14 years 13 days ago
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem
Abstract—Antenna problem is a phenomenon of plasma-induced gateoxide degradation. It directly affects manufacturability of very large scale integration (VLSI) circuits, especiall...
Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong,...