141 search results - page 8 / 29 » Layout Problems on Lattice Graphs |
ASPDAC
1998
ACM
14 years 24 days ago
1998
ACM
- In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitanc...
CIVR
2007
Springer
14 years 2 months ago
2007
Springer
Ensuring the uniqueness of trademark images and protecting their identities are the most important objectives for the trademark registration process. To prevent trademark infringe...
ISCI
2007
13 years 8 months ago
2007
Techniques for drawing graphs have proven successful in producing good layouts of undirected graphs. When nodes must be labeled however, the problem of overlapping nodes arises, p...
ICCAD
2008
IEEE
14 years 5 months ago
2008
IEEE
In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures)...
GCB
2004
Springer
14 years 1 months ago
2004
Springer
: To facilitate research in comparative genomics, sequencing projects are increasingly aimed at assembling the genomes of closely related organisms. Given two incomplete assemblies...