1658 search results - page 229 / 332 » Layout of Bayesian Networks |
ISCAS
2008
IEEE
14 years 2 months ago
2008
IEEE
— This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 µm CMOS technology. The si...
AUIC
2003
IEEE
14 years 1 months ago
2003
IEEE
There is a growing demand for the development of multi-device, adaptive user interfaces – interfaces that will run on and adapt to the characteristics of multiple display device...
DAC
1999
ACM
14 years 14 days ago
1999
ACM
In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution meth...
HICSS
1998
IEEE
14 years 12 days ago
1998
IEEE
This paper describes a generic approach to the development of a virtual reality-based user interface for a collection of digital documents. We emphasise the role of intrinsic inte...
IPPS
1998
IEEE
14 years 12 days ago
1998
IEEE
In this paper we devise an optimal deterministic algorithm for routing h-relations on-line on an N-input/output multibutterfly. The algorithm, which is obtained by generalizing th...