1658 search results - page 283 / 332 » Layout of Bayesian Networks |
ISLPED
1999
ACM
13 years 12 months ago
1999
ACM
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
HPDC
1998
IEEE
13 years 12 months ago
1998
IEEE
PAWS (Parallel Application WorkSpace) is a software infrastructure for use in connecting separate parallel applications within a component-like model. A central PAWS Controller co...
IPPS
1997
IEEE
13 years 12 months ago
1997
IEEE
Sorting is an important component of many applications, and parallel sorting algorithms have been studied extensively in the last three decades. One of the earliest parallel sorti...
VISSYM
2007
13 years 10 months ago
2007
We present TrustNeighborhoods, a security trust visualization for situational awareness on the Internet aimed at novice and intermediate users of a distributed file sharing system...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...