129 search results - page 2 / 26 » Layout synthesis for datapath designs |
113
Voted
ASPDAC
2004
ACM
15 years 9 months ago
2004
ACM
— While essential for high-performance circuit design, the custom nature of datapath components confines their use in only a few microprocessor companies. The reusability of dat...
133
Voted
ISPD
1997
ACM
15 years 8 months ago
1997
ACM
The inherent distortion of the structural regularity of VLSI datapaths after logic optimization has until now precluded dense regular layouts of optimized datapaths despite their ...
120
Voted
ICCD
2004
IEEE
16 years 21 days ago
2004
IEEE
This paper proposes a new formalism for layout-driven optimization of datapaths. It is based on preserving an arithmetic bit level representation of the arithmetic circuit portion...
134
Voted
ISVLSI
2005
IEEE
15 years 9 months ago
2005
IEEE
— Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO2) is very low. We intuit...
128
Voted
DAC
2010
ACM
15 years 4 months ago
2010
ACM
We present a technique to automatically synthesize a multithreaded in-order pipeline from a high-level unpipelined datapath specification. This work extends the previously propose...