62 search results - page 8 / 13 » Leakage Minimization Technique for Nanoscale CMOS VLSI |
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
Gate oxide tunneling current (Igate) is emerging as a key roadblock for device scaling in nanometer-scale CMOS circuits. A practical means to reduce Igate is to leverage dual Tox ...
ICCD
2003
IEEE
14 years 4 months ago
2003
IEEE
- This paper presents a precomputation-based guarding technique to reduce both dynamic and static power consumptions in CMOS VLSI circuits. More precisely, a high threshold sleep t...
ISLPED
2003
ACM
14 years 20 days ago
2003
ACM
The increasing prominence of portable systems and the need to limit power consumption and hence, heat dissipation in very high density VLSI chips have led to rapid and innovative ...
GLVLSI
2008
IEEE
14 years 1 months ago
2008
IEEE
Novel nano-scale devices have shown promising potential to overcome physical barriers faced by complementary metaloxide semiconductor (CMOS) technology in future circuit design. H...
TCAD
2008
13 years 7 months ago
2008
Abstract--Design of a suitable power gating (e.g., multithreshold CMOS or super cutoff CMOS) structure is an important and challenging task in sub-90nm VLSI circuits where leakage ...