491 search results - page 42 / 99 » Leakage power modeling and optimization in interconnection n... |
CODES
2006
IEEE
14 years 2 months ago
2006
IEEE
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
CN
2002
13 years 8 months ago
2002
In todays IP networks most of the network control and management tasks are performed at the end points. As a result, many important network functions cannot be optimized due to la...
MM
2003
ACM
14 years 1 months ago
2003
ACM
Optimizing user experience for streaming video applications on handheld devices is a significant research challenge. In this paper, we propose an integrated power management appr...
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
NOCS
2008
IEEE
14 years 2 months ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...