491 search results - page 44 / 99 » Leakage power modeling and optimization in interconnection n... |
ICCAD
2010
IEEE
13 years 6 months ago
2010
IEEE
Clock networks contribute a significant fraction of dynamic power and can be a limiting factor in high-performance CPUs and SoCs. The need for multi-objective optimization over a l...
TON
2010
13 years 6 months ago
2010
—In this paper, we investigate the maximization of the coverage time for a clustered wireless sensor network (WSN) by optimal balancing of power consumption among cluster heads (...
ICCAD
2000
IEEE
14 years 14 days ago
2000
IEEE
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
ERSA
2010
13 years 6 months ago
2010
Research in communication networks has shown that the Internet architecture is not sufficient for modern communication areas such as the interconnection networks of super computing...
SLIP
2003
ACM
14 years 1 months ago
2003
ACM
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...