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» Leakage power modeling and reduction with data retention
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ASPDAC
2004
ACM
126views Hardware» more  ASPDAC 2004»
14 years 2 months ago
High-level area and power-up current estimation considering rich cell library
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel,...
PATMOS
2007
Springer
14 years 2 months ago
Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data
In this work we consider coefficient reordering for low power realization of FIR filters on fixed-point multiply-accumulate (MAC) based architectures, such as DSP processors. Com...
Oscar Gustafsson, Saeeid Tahmasbi Oskuii, Kenny Jo...
DAC
2009
ACM
14 years 9 months ago
Analysis and mitigation of process variation impacts on Power-Attack Tolerance
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...
Lang Lin, Wayne P. Burleson
ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
14 years 3 months ago
Low power circuit design based on heterojunction tunneling transistors (HETTs)
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low ...
Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, ...
PRL
2006
121views more  PRL 2006»
13 years 8 months ago
Information-preserving hybrid data reduction based on fuzzy-rough techniques
Data reduction plays an important role in machine learning and pattern recognition with a high-dimensional data. In real-world applications data usually exists with hybrid formats...
Qinghua Hu, Daren Yu, Zongxia Xie