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» Level Shifter Design for Low Power Applications
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CCECE
2011
IEEE
12 years 9 months ago
A low power 9.5 ENOB 100MS/s pipeline ADC using correlated level shifting
—In this work the design of a low power 10-bit 100MS/s pipeline ADC is presented. Low power consumption is realized by using an optimum bit per stage resolution and also by apply...
Kambiz Nanbakhsh, Hamidreza Maghami, Samad Sheikha...
AES
2004
Springer
190views Cryptology» more  AES 2004»
14 years 3 months ago
Small Size, Low Power, Side Channel-Immune AES Coprocessor: Design and Synthesis Results
Abstract. When cryptosystems are being used in real life, hardware and software implementations themselves present a fruitful field for attacks. Side channel attacks exploit infor...
Elena Trichina, Tymur Korkishko, Kyung-Hee Lee
IPPS
2006
IEEE
14 years 3 months ago
A high level SoC power estimation based on IP modeling
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...
David Elléouet, Nathalie Julien, Dominique ...
ICA3PP
2005
Springer
14 years 3 months ago
A Low-Level Communication Library for Java HPC
Abstract. Designing a simple but powerful low-level communication library for Java HPC environments is an important task. We introduce new low-level communication library for Java ...
Sang Boem Lim, Bryan Carpenter, Geoffrey Fox, Han-...
ICCAD
2006
IEEE
110views Hardware» more  ICCAD 2006»
14 years 6 months ago
Voltage island aware floorplanning for power and timing optimization
Power consumption is a crucial concern in nanometer chip design. Researchers have shown that multiple supply voltage (MSV) is an effective method for power consumption reduction....
Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang