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MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
15 years 2 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
HT
2007
ACM
15 years 8 months ago
An agile hypertext design methodology
Customers are driving down lead times for software, especially for Web applications, to only a few months. While a number of hypertext design models exist, they do not address the...
Gary B. Wills, Noura Abbas, Rakhi Chandrasekharan,...
ICCAD
1998
IEEE
76views Hardware» more  ICCAD 1998»
15 years 8 months ago
Functional debugging of systems-on-chip
Due to the exponential growth of both design complexity and the number of gates per pin, functional debugging has emerged as a critical step in the development of a system-on-chip...
Darko Kirovski, Miodrag Potkonjak, Lisa M. Guerra
COMPSAC
2009
IEEE
15 years 2 months ago
Towards Call for Testing: An Application to User Acceptance Testing of Web Applications
1 The paper proposes a new test model, Call-For-Testing (CFT), and applies it to User Acceptance Testing (UAT) of Web Applications. Different from traditional approaches, UAT in th...
Lian Yu, Wei Zhao, Xiaofeng Di, Changzhu Kong, Wen...
LCN
2003
IEEE
15 years 9 months ago
A holistic methodology for network processor design
The GigaNetIC project aims to develop high-speed components for networking applications based on massively parallel architectures. A central part of this project is the design, ev...
Olaf Bonorden, Nikolaus Brüls, Uwe Kastens, D...