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ASYNC
2007
IEEE
132views Hardware» more  ASYNC 2007»
14 years 3 months ago
Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. Howev...
Tiberiu Chelcea, Girish Venkataramani, Seth Copen ...
BROADNETS
2007
IEEE
14 years 3 months ago
Rendezvous-based directional routing: A performance analysis
Abstract— The increased usage of directional methods of communications to improve medium reuse, network capacity, and bandwidth has prompted research into leveraging directionalit...
Bow-Nan Cheng, Murat Yuksel, Shivkumar Kalyanarama...
DATE
2007
IEEE
106views Hardware» more  DATE 2007»
14 years 3 months ago
Design closure driven delay relaxation based on convex cost network flow
Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in hi...
Chuan Lin, Aiguo Xie, Hai Zhou
EDOC
2007
IEEE
14 years 3 months ago
Model-Driven Engineering for Requirements Analysis
Requirements engineering (RE) encompasses a set of activities for eliciting, modelling, agreeing, communicating and validating requirements that precisely define the problem doma...
Benoit Baudry, Clémentine Nebut, Yves Le Tr...
ESCIENCE
2007
IEEE
14 years 3 months ago
An Integrated Grid Development Environment in Eclipse
With the proliferation of Grid computing, a large number of computational resources are available for solving complex scientific and engineering problems. Nevertheless, it is non-...
Donny Kurniawan, David Abramson