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CGO
2008
IEEE
14 years 2 months ago
Parallel-stage decoupled software pipelining
In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and ne...
Easwaran Raman, Guilherme Ottoni, Arun Raman, Matt...
CGO
2010
IEEE
14 years 1 days ago
An efficient software transactional memory using commit-time invalidation
To improve the performance of transactional memory (TM), researchers have found many eager and lazy optimizations for conflict detection, the process of determining if transaction...
Justin Emile Gottschlich, Manish Vachharajani, Jer...
ISCA
2003
IEEE
110views Hardware» more  ISCA 2003»
14 years 1 months ago
Guided Region Prefetching: A Cooperative Hardware/Software Approach
Despite large caches, main-memory access latencies still cause significant performance losses in many applications. Numerous hardware and software prefetching schemes tolerate th...
Zhenlin Wang, Doug Burger, Steven K. Reinhardt, Ka...
BMCBI
2010
163views more  BMCBI 2010»
13 years 7 months ago
DraGnET: Software for storing, managing and analyzing annotated draft genome sequence data
Background: New "next generation" DNA sequencing technologies offer individual researchers the ability to rapidly generate large amounts of genome sequence data at drama...
Stacy Duncan, Ruchita Sirkanungo, Leslie Miller, G...
ISCA
2007
IEEE
146views Hardware» more  ISCA 2007»
14 years 2 months ago
Hardware atomicity for reliable software speculation
Speculative compiler optimizations are effective in improving both single-thread performance and reducing power consumption, but their implementation introduces significant compl...
Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, ...