Sciweavers

331 search results - page 10 / 67
» Limits on Multiple Instruction Issue
Sort
View
HPCA
2005
IEEE
14 years 9 months ago
Software Directed Issue Queue Power Reduction
The issue logic of a superscalar processor dissipates a large amount of static and dynamic power. Furthermore, its power density makes it a hot-spot requiring expensive cooling sy...
Antonio González, Jaume Abella, Michael F. ...
CODES
2006
IEEE
14 years 16 days ago
Application specific forwarding network and instruction encoding for multi-pipe ASIPs
Small area and code size are two critical design issues in most of embedded system designs. In this paper, we tackle these issues by customizing forwarding networks and instructio...
Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswar...
MASCOTS
2003
13 years 10 months ago
Multipath Routing in Mobile Ad Hoc Networks: Issues and Challenges
Mobile ad hoc networks (MANETs) consist of a collection of wireless mobile nodes which dynamically exchange data among themselves without the reliance on a fixed base station or a...
Stephen Mueller, Rose P. Tsang, Dipak Ghosal
ICCD
2004
IEEE
87views Hardware» more  ICCD 2004»
14 years 5 months ago
Evaluating Techniques for Exploiting Instruction Slack
In many workloads, 25% to 50% of instructions have slack allowing them to be delayed without impacting performance. To exploit this slack, processors may implement more power-ef...
Yau Chin, John Sheu, David Brooks
ICCD
2004
IEEE
112views Hardware» more  ICCD 2004»
14 years 5 months ago
Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm
In this work, we propose a dynamic power-aware issue queue in a general-purpose microprocessor for multimedia applications. Its resources can be adapted at runtime in accordance w...
Yu Bai, R. Iris Bahar