331 search results - page 12 / 67 » Limits on Multiple Instruction Issue |
IEEEPACT
1999
IEEE
14 years 1 months ago
1999
IEEE
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
ISCA
2005
IEEE
14 years 2 months ago
2005
IEEE
RENO is a modified MIPS R10000 register renamer that uses map-table “short-circuiting” to implement dynamic versions of several well-known static optimizations: move eliminat...
ISCA
2005
IEEE
14 years 2 months ago
2005
IEEE
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
IEEEPACT
2002
IEEE
14 years 1 months ago
2002
IEEE
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...
IEEEPACT
2000
IEEE
14 years 1 months ago
2000
IEEE
Recent digital signal processors (DSPs) show a homogeneous VLIW-like data path architecture, which allows C compilers to generate efficient code. However, still some special rest...