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CORR
2008
Springer
91views Education» more  CORR 2008»
13 years 7 months ago
Taming Modal Impredicativity: Superlazy Reduction
Pure, or type-free, Linear Logic proof nets are Turing complete once cut-elimination is5 considered as computation. We introduce modal impredicativity as a new form of impredicati...
Ugo Dal Lago, Luca Roversi, Luca Vercelli
TCAD
2010
130views more  TCAD 2010»
13 years 2 months ago
On ATPG for Multiple Aggressor Crosstalk Faults
Crosstalk faults have emerged as a significant mechanism for circuit failure. Long signal nets are of particular concern because they tend to have a higher coupling capacitance to...
Kunal P. Ganeshpure, Sandip Kundu
DAGSTUHL
2006
13 years 9 months ago
DecSerFlow: Towards a Truly Declarative Service Flow Language
The need for process support in the context of web services has triggered the development of many languages, systems, and standards. Industry has been developing software solutions...
Wil M. P. van der Aalst, Maja Pesic
DATE
2000
IEEE
88views Hardware» more  DATE 2000»
14 years 4 days ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
AINA
2003
IEEE
13 years 11 months ago
Formal Verification of Condition Data Flow Diagrams for Assurance of Correct Network Protocols
Condition Data Flow Diagrams (CDFDs) are a formalized notation resulting from the integration of Yourdon Data Flow Diagrams, Petri Nets, and pre-post notation. They are used in th...
Shaoying Liu