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VLSID
2005
IEEE
139views VLSI» more  VLSID 2005»
14 years 9 months ago
Variable Input Delay CMOS Logic for Low Power Design
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
CDC
2010
IEEE
144views Control Systems» more  CDC 2010»
13 years 4 months ago
Formal analysis of piecewise affine systems through formula-guided refinement
Abstract-- We present a computational framework for identifying a set of initial states from which all trajectories of a piecewise affine (PWA) system satisfy a Linear Temporal Log...
Boyan Yordanov, Jana Tumova, Calin Belta, Ivana Ce...
SDM
2007
SIAM
104views Data Mining» more  SDM 2007»
13 years 10 months ago
Boosting Optimal Logical Patterns Using Noisy Data
We consider the supervised learning of a binary classifier from noisy observations. We use smooth boosting to linearly combine abstaining hypotheses, each of which maps a subcube...
Noam Goldberg, Chung-chieh Shan
LMCS
2007
132views more  LMCS 2007»
13 years 9 months ago
The Complexity of Model Checking Higher-Order Fixpoint Logic
Higher-Order Fixpoint Logic (HFL) is a hybrid of the simply typed λ-calculus and the modal µ-calculus. This makes it a highly expressive temporal logic that is capable of express...
Roland Axelsson, Martin Lange, Rafal Somla
JAPLL
2010
141views more  JAPLL 2010»
13 years 7 months ago
Algebraic tableau reasoning for the description logic SHOQ
Semantic web applications based on the web ontology language (OWL) often require the use of numbers in class descriptions for expressing cardinality restrictions on properties or ...
Jocelyne Faddoul, Volker Haarslev