320 search results - page 50 / 64 » Linking codesign and reuse in embedded systems design |
CISIS
2009
IEEE
2009
IEEE
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
14 years 3 months ago
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
SPAA
2004
ACM
14 years 2 months ago
2004
ACM
Given a general graph G, a fundamental problem is to find a spanning tree H that best approximates G by some measure. Often this measure is some combination of the congestion and...
ISORC
1998
IEEE
14 years 1 months ago
1998
IEEE
The Time-Triggered Architecture (TTA) provides a computing infrastructure for the design and implementation of dependable distributed embedded systems. A large real-time applicatio...
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
Existing work on testing NoC-based systems advocates to reuse the on-chip network itself as test access mechanism (TAM) to transport test data to/from embedded cores. While this m...
CODES
2007
IEEE
14 years 3 months ago
2007
IEEE
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...