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» Linking codesign and reuse in embedded systems design
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CODES
2009
IEEE
13 years 11 months ago
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
Vincenzo Rana, Srinivasan Murali, David Atienza, M...
DATE
2003
IEEE
151views Hardware» more  DATE 2003»
14 years 29 days ago
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
Adrijean Andriahantenaina, Hervé Charlery, ...
EUROMICRO
1999
IEEE
14 years 3 hour ago
Processing Requirements by Software Configuration Management
Short development life cycles, the importance of timeto-market and fast changes in technology influence the requirements engineering process. Requirements are exposed to changes d...
Ivica Crnkovic, Peter J. Funk, Magnus Larsson
RSP
2003
IEEE
132views Control Systems» more  RSP 2003»
14 years 29 days ago
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Arun Kejariwal, Nikil Dutt
CASES
2008
ACM
13 years 9 months ago
Active control and digital rights management of integrated circuit IP cores
We introduce the first approach that can actively control multiple hardware intellectual property (IP) cores used in an integrated circuit (IC). The IP rights owner(s) can remotel...
Yousra Alkabani, Farinaz Koushanfar