Sciweavers

1929 search results - page 329 / 386
» Load Balancing with Memory
Sort
View
EUROSYS
2009
ACM
14 years 6 months ago
Improving the responsiveness of internet services with automatic cache placement
The backends of today’s Internet services rely heavily on caching at various layers both to provide faster service to common requests and to reduce load on back-end components. ...
Alexander Rasmussen, Emre Kiciman, V. Benjamin Liv...
DSD
2009
IEEE
148views Hardware» more  DSD 2009»
14 years 3 months ago
SIMD Architectural Enhancements to Improve the Performance of the 2D Discrete Wavelet Transform
—The 2D Discrete Wavelet Transform (DWT) is a time-consuming kernel in many multimedia applications such as JPEG2000 and MPEG-4. The 2D DWT consists of horizontal filtering alon...
Asadollah Shahbahrami, Ben H. H. Juurlink
ARCS
2010
Springer
14 years 3 months ago
How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT
This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-ti...
Jörg Mische, Irakli Guliashvili, Sascha Uhrig...
DATE
2008
IEEE
165views Hardware» more  DATE 2008»
14 years 3 months ago
Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems
Modern embedded CPU systems rely on a growing number of software features, but this growth increases the memory footprint and increases the need for efficient instruction and data...
Ken W. Batcher, Robert A. Walker
ICC
2008
IEEE
168views Communications» more  ICC 2008»
14 years 3 months ago
Topology Control for Reliable Sensor-to-Sink Data Transport in Sensor Networks
— Wireless Sensor Networks (WSNs) are generally used for harsh environments involving military surveillance, emergency response, and habitat monitoring. Due to severe resource co...
Jiong Wang, Sirisha Medidi