1929 search results - page 335 / 386 » Load Balancing with Memory |
SPAA
2003
ACM
14 years 2 months ago
2003
ACM
The current literature offers two extremes of nonblocking software synchronization support for concurrent data structure design: intricate designs of specific structures based o...
ISCA
2002
IEEE
14 years 2 months ago
2002
IEEE
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
ICCS
2009
Springer
14 years 1 months ago
2009
Springer
Nowadays, the Grid is the focus of multiple researches. Our work is centered on Resource Management for Grids as it is an opened and current research area. Decentralized, scalable ...
ICVS
2001
Springer
14 years 1 months ago
2001
Springer
Interactive robotics demands real-time visual information about the environment. Real time vision processing, however, places a heavy load on the robot’s limited resources, and m...
MICRO
2000
IEEE
14 years 1 months ago
2000
IEEE
Silent store instructions write values that exactly match the values that are already stored at the memory address that is being written. A recent study reveals that significant ...