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MICRO
2005
IEEE
114views Hardware» more  MICRO 2005»
15 years 8 months ago
Address-Indexed Memory Disambiguation and Store-to-Load Forwarding
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
Sam S. Stone, Kevin M. Woley, Matthew I. Frank
HPCA
2005
IEEE
16 years 2 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
ICANN
2007
Springer
15 years 6 months ago
Classifying EEG Data into Different Memory Loads Across Subjects
Abstract. In this paper we consider the question of whether it is possible to classify n-back EEG data into different memory loads across subjects. To capture relevant information ...
Liang Wu, Predrag Neskovic
123
Voted
PPOPP
2009
ACM
16 years 3 months ago
Idempotent work stealing
Load balancing is a technique which allows efficient parallelization of irregular workloads, and a key component of many applications and parallelizing runtimes. Work-stealing is ...
Maged M. Michael, Martin T. Vechev, Vijay A. Saras...