141 search results - page 16 / 29 » Load Execution Latency Reduction |
FPL
2009
Springer
14 years 1 months ago
2009
Springer
This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a...
MICRO
2009
IEEE
14 years 3 months ago
2009
IEEE
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
HPCA
2001
IEEE
14 years 9 months ago
2001
IEEE
Mispredicted branches and loads that miss in the cache cause the majority of retirement stalls experienced by sequential processors; we call these critical instructions. Despite t...
ACSC
2005
IEEE
14 years 2 months ago
2005
IEEE
The Address Recalculation Pipeline is a hardware architecture designed to reduce the end-to-end latency suffered by immersive Head Mounted Display virtual reality systems. A deman...
ETFA
2008
IEEE
14 years 3 months ago
2008
IEEE
We present a method for fine grain QoS control of multimedia applications. This method takes as input an application software composed of actions. The execution times are unknown...