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IPPS
2000
IEEE
13 years 12 months ago
Reducing Ownership Overhead for Load-Store Sequences in Cache-Coherent Multiprocessors
Parallel programs that modify shared data in a cachecoherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisiti...
Jim Nilsson, Fredrik Dahlgren
CGO
2006
IEEE
14 years 1 months ago
A Self-Repairing Prefetcher in an Event-Driven Dynamic Optimization Framework
Software prefetching has been demonstrated as a powerful technique to tolerate long load latencies. However, to be effective, prefetching must target the most critical (frequently...
Weifeng Zhang, Brad Calder, Dean M. Tullsen
ASPDAC
2009
ACM
102views Hardware» more  ASPDAC 2009»
14 years 2 months ago
Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction
Power delivery network (PDN) is a distributed RLC network with its dominant resonance frequency in the low-to-middle frequency range. Though high-performance chips’ working freq...
Yiyu Shi, Jinjun Xiong, Howard Chen, Lei He
ESTIMEDIA
2009
Springer
13 years 5 months ago
Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications
The increasing demand for low power and high performance multimedia embedded systems has motivated the need for effective solutions to satisfy application bandwidth and latency req...
Luis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, ...
VTS
2002
IEEE
138views Hardware» more  VTS 2002»
14 years 11 days ago
Test Power Reduction through Minimization of Scan Chain Transitions
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...