141 search results - page 7 / 29 » Load Execution Latency Reduction |
HPCA
2008
IEEE
14 years 7 months ago
2008
IEEE
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
IPPS
2003
IEEE
14 years 22 days ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Power has become a critical concern for battery-driven computing systems, on which many applications that are run are interactive. System-level voltage scaling techniques, such as...
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
EMSOFT
2009
Springer
14 years 2 months ago
2009
Springer
Scratchpads have been widely proposed as an alternative to caches for embedded systems. Advantages of scratchpads include reduced energy consumption in comparison to a cache and a...