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ICCAD
2009
IEEE
133views Hardware» more  ICCAD 2009»
14 years 12 months ago
A parallel preconditioning strategy for efficient transistor-level circuit simulation
A parallel computing approach for large-scale SPICE-accurate circuit simulation is described that is based on a new preconditioned iterative solver. The preconditioner involves the...
Heidi Thornquist, Eric R. Keiter, Robert J. Hoekst...
120
Voted
IPPS
1996
IEEE
15 years 6 months ago
Practical Parallel Algorithms for Dynamic Data Redistribution, Median Finding, and Selection
A common statistical problem is that of nding the median element in a set of data. This paper presents a fastand portable parallel algorithm for nding the median given a set of el...
David A. Bader, Joseph JáJá
112
Voted
SIGGRAPH
2000
ACM
15 years 6 months ago
Pomegranate: a fully scalable graphics architecture
Pomegranate is a parallel hardware architecture for polygon rendering that provides scalable input bandwidth, triangle rate, pixel rate, texture memory and display bandwidth while...
Matthew Eldridge, Homan Igehy, Pat Hanrahan
208
Voted
ISCA
2002
IEEE
174views Hardware» more  ISCA 2002»
15 years 1 months ago
Efficient Task Partitioning Algorithms for Distributed Shared Memory Systems
In this paper, we consider the tree task graphs which arise from many important programming paradigms such as divide and conquer, branch and bound etc., and the linear task-graphs...
Sibabrata Ray, Hong Jiang
163
Voted
ICDCS
1996
IEEE
15 years 6 months ago
Dynamic Scheduling Strategies for Shared-memory Multiprocessors
Efficiently scheduling parallel tasks on to the processors of a shared-memory multiprocessor is critical to achieving high performance. Given perfect information at compile-time, ...
Babak Hamidzadeh, David J. Lilja