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QEST
2006
IEEE
14 years 4 months ago
Modeling Fiber Delay Loops in an All Optical Switch
We analyze the effect of a few fiber delay loops on the number of deflections in an all optical packet switch. The switch is based on the ROMEO architecture developed by Alcatel...
Ana Busic, Mouad Ben Mamoun, Jean-Michel Fourneau
WETICE
2006
IEEE
14 years 4 months ago
Multi-Dimensional Performance Framework for Enterprise Knowledge Infrastructures
— Within service-oriented business environments, the non-routine processing of requests requires a greater degree of social interaction and learning in order to achieve an effect...
Joe Bolinger, Jay Ramanathan
SAC
2006
ACM
14 years 4 months ago
Building the functional performance model of a processor
In this paper, we present an efficient procedure for building a piecewise linear function approximation of the speed function of a processor with hierarchical memory structure. Th...
Alexey L. Lastovetsky, Ravi Reddy, Robert Higgins
CGO
2005
IEEE
14 years 4 months ago
A Progressive Register Allocator for Irregular Architectures
Register allocation is one of the most important optimizations a compiler performs. Conventional graphcoloring based register allocators are fast and do well on regular, RISC-like...
David Koes, Seth Copen Goldstein
HICSS
2005
IEEE
145views Biometrics» more  HICSS 2005»
14 years 4 months ago
Interoperability in E-Government: More than Just Smart Middleware
According to Layne and Lee (2001), electronic Government (e-Government, e-Gov) progresses towards higher levels of integration and interoperability among and between government le...
Hans Jochen Scholl
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