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CODES
2007
IEEE
14 years 1 months ago
Synchronization after design refinements with sensitive delay elements
The synchronous computational model with its simple computation and communication mechanism makes it easy to describe, simulate and formally verify synchronous embedded systems at...
Tarvo Raudvere, Ingo Sander, Axel Jantsch
ACSD
2004
IEEE
124views Hardware» more  ACSD 2004»
14 years 1 months ago
A Behavioral Type Inference System for Compositional System-on-Chip Design
The design productivity gap has been recognized by the semiconductor industry as one of the major threats to the continued growth of system-on-chips and embedded systems. Ad-hoc s...
Jean-Pierre Talpin, David Berner, Sandeep K. Shukl...
CGO
2004
IEEE
14 years 1 months ago
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing ...
Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv...
EMSOFT
2006
Springer
14 years 1 months ago
Polychronous mode automata
Among related synchronous programming principles, the model of computation of the Polychrony workbench stands out by its capability to give high-level description of systems where...
Jean-Pierre Talpin, Christian Brunette, Thierry Ga...
CASES
2001
ACM
14 years 1 months ago
Patchable instruction ROM architecture
Increased systems level integration has meant the movement of many traditionally off chip components onto a single chip including a processor, instruction storage, data path, and ...
Timothy Sherwood, Brad Calder