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DATE
2005
IEEE
97views Hardware» more  DATE 2005»
14 years 1 months ago
Synchronization Processor Synthesis for Latency Insensitive Systems
In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carlon...
Pierre Bomel, Eric Martin, Emmanuel Boutillon
DFT
1994
IEEE
121views VLSI» more  DFT 1994»
14 years 12 days ago
Reconfiguration in 3D Meshes
The 1: track model for fault tolerant 2 0 processor arrays is extended to 30 mesh architectures. Non-intersecting, continuous, straight and non-near miss compensation paths are co...
Anuj Chandra, Rami G. Melhem
GRAPHICSINTERFACE
2001
13 years 9 months ago
Universal Rendering Sequences for Transparent Vertex Caching of Progressive Meshes
We present methods to generate rendering sequences for triangle meshes which preserve mesh locality as much as possible. This is useful for maximizing vertex reuse when rendering ...
Alexander Bogomjakov, Craig Gotsman
ENTCS
2007
111views more  ENTCS 2007»
13 years 8 months ago
Compositional State Space Reduction Using Untangled Actions
We propose a compositional technique for efficient verification of networks of parallel processes. It is based on an automatic analysis of LTSs of individual processes (using a f...
Xu Wang, Marta Z. Kwiatkowska
NN
2000
Springer
123views Neural Networks» more  NN 2000»
13 years 8 months ago
Visual cortical mechanisms of perceptual grouping: interacting layers, networks, columns, and maps
The visual cortex has a laminar organization whose circuits form functional columns in cortical maps. How this laminar architecture supports visual percepts is not well understood...
William D. Ross, Stephen Grossberg, Ennio Mingolla