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MASCOTS
2004
13 years 9 months ago
Performance Engineering with the UML Profile for Schedulability, Performance and Time: A Case Study
We describe the application of a performance engineering methodology based on UML diagrams with annotations taken from the Profile for Schedulability, Performance and Time. The me...
Andrew J. Bennett, A. J. Field
SIGMETRICS
1992
ACM
128views Hardware» more  SIGMETRICS 1992»
13 years 11 months ago
MemSpy: Analyzing Memory System Bottlenecks in Programs
To cope with the increasing difference between processor and main memory speeds, modern computer systems use deep memory hierarchies. In the presence of such hierarchies, the perf...
Margaret Martonosi, Anoop Gupta, Thomas E. Anderso...
DATE
2008
IEEE
171views Hardware» more  DATE 2008»
14 years 2 months ago
Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip
Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor systemon-chip. An external memory that is shared between processors is a bottl...
Arno Moonen, Marco Bekooij, Rene van den Berg, Jef...
RIDE
1998
IEEE
13 years 12 months ago
Performance Enhancement Using Intra-server Caching in a Continuous Media Server
Continuity of stream playback is the crucial constraint in designing a continuous media server. From a distributed memory architectural model developed earlier, we found that ther...
Chutimet Srinilta, Alok N. Choudhary
ASPLOS
1991
ACM
13 years 11 months ago
The Cache Performance and Optimizations of Blocked Algorithms
Blocking is a well-known optimization technique for improving the effectiveness of memory hierarchies. Instead of operating on entire rows or columns of an array, blocked algorith...
Monica S. Lam, Edward E. Rothberg, Michael E. Wolf