Sciweavers

10 search results - page 2 / 2
» Lock Coarsening: Eliminating Lock Overhead in Automatically ...
Sort
View
PLDI
2009
ACM
14 years 2 months ago
Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory
Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performa...
Mojtaba Mehrara, Jeff Hao, Po-Chun Hsu, Scott A. M...
ASPLOS
2008
ACM
13 years 9 months ago
Optimistic parallelism benefits from data partitioning
Recent studies of irregular applications such as finite-element mesh generators and data-clustering codes have shown that these applications have a generalized data parallelism ar...
Milind Kulkarni, Keshav Pingali, Ganesh Ramanaraya...
POPL
2009
ACM
14 years 8 months ago
The theory of deadlock avoidance via discrete control
Deadlock in multithreaded programs is an increasingly important problem as ubiquitous multicore architectures force parallelization upon an ever wider range of software. This pape...
Manjunath Kudlur, Scott A. Mahlke, Stéphane...
IPPS
2007
IEEE
14 years 1 months ago
Formal Analysis for Debugging and Performance Optimization of MPI
High-end computing is universally recognized to be a strategic tool for leadership in science and technology. A significant portion of high-end computing is conducted on clusters...
Ganesh Gopalakrishnan, Robert M. Kirby
HPCA
2008
IEEE
14 years 7 months ago
Thread-safe dynamic binary translation using transactional memory
Dynamic binary translation (DBT) is a runtime instrumentation technique commonly used to support profiling, optimization, secure execution, and bug detection tools for application...
JaeWoong Chung, Michael Dalton, Hari Kannan, Chris...