195 search results - page 24 / 39 » Lock-Free Parallel Algorithms: An Experimental Study |
ICASSP
2008
IEEE
14 years 2 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
GCC
2004
Springer
14 years 1 months ago
2004
Springer
This paper addresses the dynamic scheduling of moldable jobs with QoS demands (soft-deadlines) in multiclusters. A moldable job can be run on a variable number of resources. Three ...
ICS
1999
Tsinghua U.
13 years 12 months ago
1999
Tsinghua U.
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
CEC
2011
IEEE
12 years 7 months ago
2011
IEEE
—Multiobjective optimization problems have been widely addressed using evolutionary computation techniques. However, when dealing with more than three conflicting objectives (th...
CPAIOR
2006
Springer
13 years 11 months ago
2006
Springer
Temporal planning (TP) is notoriously difficult because it requires to solve a propositional STRIPS planning problem with temporal constraints. In this paper, we propose an efficie...