195 search results - page 24 / 39 » Lock-Free Parallel Algorithms: An Experimental Study |
129
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ICASSP
2008
IEEE
15 years 9 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
150
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GCC
2004
Springer
15 years 8 months ago
2004
Springer
This paper addresses the dynamic scheduling of moldable jobs with QoS demands (soft-deadlines) in multiclusters. A moldable job can be run on a variable number of resources. Three ...
134
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ICS
1999
Tsinghua U.
15 years 7 months ago
1999
Tsinghua U.
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
109
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CEC
2011
IEEE
14 years 3 months ago
2011
IEEE
—Multiobjective optimization problems have been widely addressed using evolutionary computation techniques. However, when dealing with more than three conflicting objectives (th...
116
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CPAIOR
2006
Springer
15 years 7 months ago
2006
Springer
Temporal planning (TP) is notoriously difficult because it requires to solve a propositional STRIPS planning problem with temporal constraints. In this paper, we propose an efficie...