Sciweavers

2291 search results - page 439 / 459
» Logic Programming and Model Checking
Sort
View
DATE
2006
IEEE
124views Hardware» more  DATE 2006»
14 years 1 months ago
Timing-driven cell layout de-compaction for yield optimization by critical area minimization
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard ...
Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
ICDCS
2005
IEEE
14 years 1 months ago
Supporting Live Development of SOAP and CORBA Servers
We present middleware for a Server Development Environment that facilitates live development of SOAP and CORBA servers. As the underlying implementation platform, we use JPie, a t...
Sajeeva L. Pallemulle, Kenneth J. Goldman, Brandon...
HPCA
2011
IEEE
12 years 11 months ago
Calvin: Deterministic or not? Free will to choose
Most shared memory systems maximize performance by unpredictably resolving memory races. Unpredictable memory races can lead to nondeterminism in parallel programs, which can suff...
Derek Hower, Polina Dudnik, Mark D. Hill, David A....
CADE
2005
Springer
14 years 7 months ago
Privacy-Sensitive Information Flow with JML
In today's society, people have very little control over what kinds of personal data are collected and stored by various agencies in both the private and public sectors. We de...
Guillaume Dufay, Amy P. Felty, Stan Matwin
CF
2006
ACM
13 years 11 months ago
Landing openMP on cyclops-64: an efficient mapping of openMP to a many-core system-on-a-chip
This paper presents our experience mapping OpenMP parallel programming model to the IBM Cyclops-64 (C64) architecture. The C64 employs a many-core-on-a-chip design that integrates...
Juan del Cuvillo, Weirong Zhu, Guang R. Gao