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» Logic design for low-voltage low-power CMOS circuits
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ARITH
2003
IEEE
14 years 23 days ago
On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge
In this paper we investigate the implementation of basic arithmetic functions, such as addition and multiplication, in Single Electron Tunneling (SET) technology. First, we descri...
Sorin Cotofana, Casper Lageweg, Stamatis Vassiliad...
TC
1998
13 years 7 months ago
Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices
—This paper describes a new signed-digit full adder (SDFA) circuit consisting of resonant-tunneling diodes (RTDs) and metal-oxide semiconductor field effect transistors (MOSFETs)...
Alejandro F. González, Pinaki Mazumder
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 1 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
DAC
2005
ACM
13 years 9 months ago
Design methodology for IC manufacturability based on regular logic-bricks
Implementing logic blocks in an integrated circuit in terms of repeating or regular geometry patterns [6,7] can provide significant advantages in terms of manufacturability and de...
V. Kheterpal, V. Rovner, T. G. Hersan, D. Motiani,...
ICIP
2004
IEEE
14 years 9 months ago
An implemented architecture of deblocking filter for H.264/AVC
H.264/AVC is a new international standard for the compression of natural video images, in which a deblocking filter has been adopted to remove blocking artifacts. In this paper, w...
Bin Sheng, Wen Gao, Di Wu