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» Logic design for low-voltage low-power CMOS circuits
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DAC
2004
ACM
14 years 2 months ago
Low voltage swing logic circuits for a Pentium 4 processor integer core
The Pentium® 4 processor architecture uses a 2x frequency core clock[1] to implement low latency integer ops. Low Voltage Swing logic circuits implemented in 90nm technology[2] m...
Daniel J. Deleganes, Micah Barany, George Geannopo...
ISQED
2005
IEEE
169views Hardware» more  ISQED 2005»
14 years 2 months ago
ASLIC: A Low Power CMOS Analog Circuit Design Automation
This paper proposes an efficient automation platform that provides fast and reliable path to analog circuit design for desired specifications. Circuit heuristics and hierarchy a...
Jihyun Lee, Yong-Bin Kim
ENGL
2007
118views more  ENGL 2007»
13 years 8 months ago
Design of Low Power CMOS Crystal Oscillator with Tuning Capacitors
—A low power CMOS crystal oscillator was proposed with high accuracy by tuning capacitors. Based on the analysis concerning power consumption, start-up time, and frequency stabil...
Shun Yao, Hengfang Zhu, Xiaobo Wu
SBCCI
2003
ACM
160views VLSI» more  SBCCI 2003»
14 years 1 months ago
Novel Design Methodology for High-Performance XOR-XNOR Circuit Design
As we scale down to deep submicron (DSM) technology, noise is becoming a metric of equal importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequen...
Sumeer Goel, Mohamed A. Elgamel, Magdy A. Bayoumi
ISLPED
1997
ACM
91views Hardware» more  ISLPED 1997»
14 years 3 days ago
Fully depleted CMOS/SOI device design guidelines for low power applications
In this paper we report the fully depleted CMOS/SOI device design guidelines for low power applications. Optimal technology, device and circuit parameters are discussed and compar...
Srinivasa R. Banna, Philip C. H. Chan, Mansun Chan...