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MSE
1999
IEEE
118views Hardware» more  MSE 1999»
14 years 1 months ago
Training IP Creators and Integrators
Intellectual property IP blocks are being created for reuse and marketed as a means of reducing the development time of complex designs. This in turn leads to a reduction in time ...
Donald W. Bouldin, Senthil Natarajan, Benjamin A. ...
TABLEAUX
2005
Springer
14 years 2 months ago
A Tableau-Based Explainer for DL Subsumption
This paper describes the implementation of a tableau-based reasoning component which is capable of providing quasi natural language explanations for subsumptions within ALEHFR+ TBo...
Thorsten Liebig, Michael Halfmann
DEDS
2000
83views more  DEDS 2000»
13 years 8 months ago
Synthesis of Discrete-Event Controllers Based on the Signal Environment
In this paper, we present the integration of controller synthesis techniques in the SIGNAL environment through the description of a tool dedicated to the incremental construction o...
Hervé Marchand, Patricia Bournai, Michel Le...
TACAS
1998
Springer
81views Algorithms» more  TACAS 1998»
14 years 1 months ago
Formal Design and Analysis of a Gear Controller
In this paper, we report on an application of the validation and veri cation tool kit Uppaal in the design and analysis of a prototype gear controller, carried out in a joint proje...
Magnus Lindahl, Paul Pettersson, Wang Yi
DATE
2009
IEEE
118views Hardware» more  DATE 2009»
14 years 3 months ago
Limiting the number of dirty cache lines
Abstract—Caches often employ write-back instead of writethrough, since write-back avoids unnecessary transfers for multiple writes to the same block. For several reasons, however...
Pepijn J. de Langen, Ben H. H. Juurlink