: It is claimed that human inferential apparatus offers interesting ground in order to consider the intuitions of artificial intelligence researchers about the inference patterns a...
An approach for stuck-at-i and delay-fault testing of redundant circuits without modifying the logic is proposed. The only requirement is the ability to control both phases of eac...
Luciano Lavagno, Antonio Lioy, Michael Kishinevsky
This paper presents a methodology for production-time testing of (uncustomized) segmented channel eld programmable gate arrays (FPGAs) such as those manufactured by Actel [1]. Th...
This paper addresses the problem of compacting test responses in the presence of unknowns at the input of the compactor by exploiting the capabilities of well-known error detectio...
Janak H. Patel, Steven S. Lumetta, Sudhakar M. Red...
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...