ct This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduc...
In the paper, an evolutionary approach to test generation for functional BIST is considered. The aim of the proposed scheme is to minimize the test data volume by allowing the dev...
Y. A. Skobtsov, D. E. Ivanov, V. Y. Skobtsov, Raim...
Reliability of logic circuits is emerging as an important concern that may limit the benefits of continued scaling of process technology and the emergence of future technology al...
We study the definability of constraint satisfaction problems (CSP) in various fixed-point and infinitary logics. We show that testing the solvability of systems of equations over...
— Web script crashes and malformed dynamically-generated web pages are common errors, and they seriously impact the usability of web applications. Current tools for web-page vali...
Shay Artzi, Adam Kiezun, Julian Dolby, Frank Tip, ...