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ITC
2003
IEEE
176views Hardware» more  ITC 2003»
14 years 27 days ago
Instruction Based BIST for Board/System Level Test of External Memories and Internconnects
ct This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduc...
Olivier Caty, Ismet Bayraktaroglu, Amitava Majumda...
CORR
2010
Springer
152views Education» more  CORR 2010»
13 years 5 months ago
Evolutionary Approach to Test Generation for Functional BIST
In the paper, an evolutionary approach to test generation for functional BIST is considered. The aim of the proposed scheme is to minimize the test data volume by allowing the dev...
Y. A. Skobtsov, D. E. Ivanov, V. Y. Skobtsov, Raim...
DATE
2007
IEEE
102views Hardware» more  DATE 2007»
14 years 1 months ago
Accurate and scalable reliability analysis of logic circuits
Reliability of logic circuits is emerging as an important concern that may limit the benefits of continued scaling of process technology and the emergence of future technology al...
Mihir R. Choudhury, Kartik Mohanram
ICALP
2007
Springer
13 years 11 months ago
Affine Systems of Equations and Counting Infinitary Logic
We study the definability of constraint satisfaction problems (CSP) in various fixed-point and infinitary logics. We show that testing the solvability of systems of equations over...
Albert Atserias, Andrei A. Bulatov, Anuj Dawar
TSE
2010
161views more  TSE 2010»
13 years 6 months ago
Finding Bugs in Web Applications Using Dynamic Test Generation and Explicit-State Model Checking
— Web script crashes and malformed dynamically-generated web pages are common errors, and they seriously impact the usability of web applications. Current tools for web-page vali...
Shay Artzi, Adam Kiezun, Julian Dolby, Frank Tip, ...