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ICCAD
1993
IEEE
81views Hardware» more  ICCAD 1993»
14 years 25 days ago
Inverter minimization in multi-level logic networks
In this paper, we look at the problem of inverter minimization in multi-level logic networks. The network is specified in terms of a set of base functions and the inversion opera...
Alok Jain, Randal E. Bryant
FASE
2008
Springer
13 years 10 months ago
A Model Checking Approach for Verifying COWS Specifications
We introduce a logical verification framework for checking functional properties of service-oriented applications formally specified using the service specification language COWS. ...
Alessandro Fantechi, Stefania Gnesi, Alessandro La...
ARTS
1999
Springer
14 years 1 months ago
Quantitative Program Logic and Performance in Probabilistic Distributed Algorithms
In this paper we show how quantitative program logic [14] provides a formal framework in which to promote standard techniques of program analysis to a context where probability and...
Annabelle McIver
VLSID
2007
IEEE
108views VLSI» more  VLSID 2007»
14 years 9 months ago
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET mode...
Feng Wang 0004, Yuan Xie, R. Rajaraman, Balaji Vai...
DLOG
2007
13 years 11 months ago
Distributed Description Logics Revisited
Distributed Description Logics (DDLs) is a KR formalism that enables reasoning with multiple ontologies interconnected by directional semantic mapping (bridge rules). DDLs capture ...
Martin Homola